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GATE digital logic: 5 practice questions with answers

By the PrepMatic team · Updated 9 Oct 2026 · 4 min read

Digital Logic is a compact section of the GATE CS paper, and it is mostly procedural: minimise a function, design with multiplexers, read a counter, handle number representations. The ideas return in computer organisation, so time here pays twice. The five original questions below use the five patterns you will see most often.

What GATE tests in digital logic

Digital Logic is a section in the GATE 2027 CS paper; confirm the revised topic list on the official syllabus page. The standard content is Boolean algebra, K-map minimisation, combinational circuits (adders, multiplexers, decoders), sequential circuits (latches, flip-flops, counters, registers) and number representation with computer arithmetic. The real paper also has MSQ and NAT questions; all five below are MCQ.

Practice questions

Question 1

The minimum sum-of-products expression for f(A, B, C, D) = Σm(0, 1, 2, 5, 8, 9, 10), with A as the most significant bit, contains how many literals in total?

• A. 5
• B. 6
• C. 7
• D. 8

Question 2

Two 8-bit two's complement numbers, 01101011 and 00101101, are added. Which one of the following is correct?

• A. The sum is +152 and no overflow occurs.
• B. The 8-bit result represents −104 and no overflow occurs.
• C. The result 10011000 represents +152 and overflow occurs.
• D. The 8-bit result represents −104 and overflow occurs.

Question 3

A 4-bit binary ripple counter (Q3 is the most significant bit) has an asynchronous clear that is activated as soon as a NAND gate with inputs Q3 and Q1 sees both inputs equal to 1. The modulus of the counter is:

• A. 10
• B. 6
• C. 8
• D. 12

Question 4

The function f(A, B, C) = Σm(1, 2, 6, 7) is implemented using a 4-to-1 multiplexer with A and B as the select inputs (A is the more significant select). The data inputs I0, I1, I2 and I3 are, respectively:

• A. C′, C, 1, 0
• B. C, C′, 0, 1
• C. C, C′, 1, 0
• D. 0, 1, C, C′

Question 5

In a synchronous circuit, a flip-flop has a clock-to-output delay of 2 ns and a setup time of 1 ns. The combinational logic between two flip-flops has a worst-case delay of 6 ns. Ignoring clock skew and hold time, the maximum clock frequency is closest to:

• A. 111 MHz
• B. 100 MHz
• C. 125 MHz
• D. 143 MHz

Answers and explanations

1. C. The prime implicants are B′C′ (covers minterms 0, 1, 8, 9), B′D′ (covers 0, 2, 8, 10) and A′C′D (covers 1, 5). Minterm 5 is covered only by A′C′D, minterm 2 only by B′D′, and minterm 9 only by B′C′, so all three are essential. The minimal form is f = B′C′ + B′D′ + A′C′D, with 2 + 2 + 3 = 7 literals.
2. D. 01101011 is +107 and 00101101 is +45, so the true sum is +152, which is larger than the 8-bit maximum of +127. The stored result is 10011000, which as a two's complement number is 152 − 256 = −104. Adding two positive numbers and getting a negative result signals overflow.
3. A. The count rises from 0000 until Q3 and Q1 are both 1 for the first time. That happens at 1010 (decimal 10), where the clear fires and the counter returns to 0000. The stable states are 0 to 9, so the modulus is 10. State 1010 appears only momentarily, as in the classic decade counter.
4. B. Group the minterms by AB. For AB = 00 (minterms 0, 1) f = C, so I0 = C. For AB = 01 (minterms 2, 3) only minterm 2 is present, so I1 = C′. For AB = 10 (minterms 4, 5) none are present, so I2 = 0. For AB = 11 (minterms 6, 7) both are present, so I3 = 1.
5. A. The clock period must cover clock-to-output delay, combinational delay and setup time: T ≥ 2 + 6 + 1 = 9 ns. The maximum frequency is 1 / 9 ns ≈ 111 MHz. Option C (125 MHz) leaves out the setup time, and option D (143 MHz) leaves out the clock-to-output delay.

How to prepare digital logic

• Be fluent with K-maps up to four variables. List the prime implicants, mark the essential ones, then cover what remains. Learn don't-cares and how to read a product-of-sums answer from the zeros.
• Know the number systems cold: two's complement range −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1, the overflow rule (carry into the sign bit differs from carry out of it), sign extension, Gray code, BCD and the IEEE 754 single-precision layout (1 sign, 8 exponent with bias 127, 23 mantissa bits).
• Design with multiplexers and decoders by one method: use the Shannon expansion on the select variables and read the data inputs from the remaining variables, as in Question 4.
• Practise sequential circuits by writing the state table. For any counter or shift register, list the states from the initial value until the sequence repeats. That catches the modulus and "state after k pulses" questions.
• Learn the timing formulas: minimum clock period = clock-to-Q + combinational delay + setup, plus the hold-time condition and the delay of ripple-carry versus carry-lookahead adders.

Digital logic leads straight into computer organisation, and EC and EE aspirants meet related ideas in digital circuits for EC. The GATE CSE preparation guide shows how to sequence the ten CS sections.

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