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GATE EC digital circuits: 5 practice questions
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Digital Circuits is a section of the GATE EC paper, and the 2027 description widens it beyond gates and flip-flops to include data converters, memories and computer organisation. That makes it a bridge between the electronics sections and the computing ideas that CS students meet. The five original questions below show that range: conversion, memory sizing, sequential design, hazards and address decoding.
What GATE tests in EC digital circuits
The GATE 2027 EC syllabus lists Digital Circuits as a section that includes data converters, memories and computer organisation. Confirm the full list on the official syllabus page. The usual content is Boolean algebra and minimisation, combinational circuits (adders, multiplexers, decoders), sequential circuits (flip-flops, counters, shift registers, state machines), logic families, ADCs and DACs, and memory types.
Questions are short and numerical or analytical: the output of a converter, the number of chips for a memory, the sequence of a counter, whether a circuit has a hazard, and what an address range implies. The real paper has MCQ, MSQ and NAT questions. All five below are MCQ. If you are a CS aspirant, the sibling page is GATE digital logic.
Practice questions
Question 1
A 10-bit DAC gives a full-scale output of 10.23 V when all input bits are 1, so each least significant bit step equals 10 mV. The output for the input code 0110010000 is:
- A. 2.56 V
- B. 3.20 V
- C. 4.00 V
- D. 6.25 V
Question 2
A memory of 16K × 8 bits is built from chips that are each 4K × 4 bits. The number of chips needed is:
- A. 2
- B. 4
- C. 6
- D. 8
Question 3
A 4-bit Johnson (twisted-ring) counter shifts to the right on each clock pulse, and the complement of the last (rightmost) flip-flop output is fed to the first (leftmost) flip-flop input. Starting from 0000, the state after 6 clock pulses is:
- A. 0011
- B. 0111
- C. 0001
- D. 1100
Question 4
The function F = AB + A′C can show a static-1 hazard when B = C = 1 and A changes. The hazard is removed, without changing the function, by adding the product term:
- A. AC
- B. BC
- C. A′B
- D. B′C′
Question 5
On a processor with a 16-bit address bus, a memory chip responds to the addresses 8000H to BFFFH. The capacity of the chip is:
- A. 2 KB
- B. 4 KB
- C. 8 KB
- D. 16 KB
Answers and explanations
- C. Convert the code to decimal: 0110010000 has bits worth 256, 128 and 16 set, so it equals 400. The output is 400 × 10 mV = 4.00 V. The full-scale value corresponds to code 1023 (10.23 V), which confirms the 10 mV step.
- D. To reach 16K words from 4K-word chips you need 16/4 = 4 chips in a row. To reach 8 bits from 4-bit chips you need 8/4 = 2 chips side by side. The total is 4 × 2 = 8 chips. The 16K words need 14 address lines, of which 12 go to the chips and 2 feed a decoder.
- A. The sequence from 0000 is 1000, 1100, 1110, 1111, 0111, 0011. After 6 pulses the state is 0011. A Johnson counter with n flip-flops cycles through 2n states, which is 8 here, so the sequence repeats after 8 pulses.
- B. When B = C = 1, F = A + A′ = 1, but the two product terms hand over from AB to A′C as A changes, which can cause a momentary glitch. Adding the consensus term BC holds the output at 1 throughout and leaves the function unchanged. The other terms alter the function: AC would make F = 1 for A = 1, B = 0, C = 1, where F was 0.
- D. The size is the end address minus the start address plus 1: BFFFH − 8000H + 1 = 4000H = 16384 bytes = 16 KB. The chip needs 14 address lines. The top two lines are A15 = 1 and A14 = 0 for chip selection.
How to prepare EC digital circuits
- Do a daily set of Boolean simplification and K-map problems until they take under two minutes. They support most other digital questions.
- Learn the sequential design cycle: state diagram, state table, flip-flop excitation tables (SR, JK, D, T), then logic. Practise reading a given circuit back into a state table.
- Memorise counter variants: ripple, synchronous, ring, Johnson and mod-N with asynchronous clear. For each, know the number of states and the sequence.
- For converters, know the formulas: resolution = full scale / (2ⁿ − 1) or / 2ⁿ depending on the convention the question states, quantisation error of half an LSB, and the working of flash, successive approximation and dual-slope ADCs.
- Practise memory arithmetic on paper: words × bits, number of chips, address lines, and decoder design for a memory map. State the answer in the units asked.
- Treat logic families as a separate revision block: noise margin, fan-out and propagation delay for TTL, CMOS and ECL.
The paper's neighbouring electronics section is analog circuits, and the same signal chain continues into communications. The GATE ECE preparation guide covers the order and weight of all eight EC sections.
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