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GATE computer organization: 5 practice questions

By the PrepMatic team · Updated 9 Oct 2026 · 4 min read

Computer Organization and Architecture is a numerical section of the GATE CS paper: cache sizes, address bits, pipeline speed-up, instruction encoding and I/O transfer rates. The questions give you a configuration and ask for one derived quantity, so the marks go to the student who writes each step in the right units. The five original questions below are typical of the section.

What GATE tests in computer organisation

The GATE 2027 CS paper names this section Computer Organization and Architecture, and its description includes cache mapping, DMA and pipeline hazards. Confirm the full revised list on the official syllabus page. Other usual topics are machine instructions and addressing modes, ALU and data path, control unit design, memory hierarchy, and I/O interfaces.

Question types include cache address breakdowns (tag, index, offset), average memory access time, pipeline CPI with hazards, instruction format and opcode expansion, interrupt and DMA timing, and speed-up. The real paper also has MSQ and NAT questions, where the unit must be exactly right. All five below are MCQ.

Practice questions

Question 1

A 32 KB cache is 4-way set associative with a block size of 64 bytes. The processor generates 32-bit physical addresses. The number of tag bits in each cache line is:

• A. 17
• B. 18
• C. 19
• D. 20

Question 2

A 5-stage pipeline has an ideal CPI of 1. 25% of the instructions are branches, 60% of the branches are taken, and each taken branch causes a 2-cycle stall. Not-taken branches cause no stall, and there are no other hazards. The average CPI is:

• A. 1.15
• B. 1.50
• C. 1.60
• D. 1.30

Question 3

A processor has 16-bit instructions in the format: 4-bit opcode, then three 4-bit operand fields. Fourteen instructions use three operands. The two opcode values left unused are expanded, using the third operand field as extra opcode bits, to encode two-operand instructions. The maximum number of two-operand instructions that can be encoded is:

• A. 32
• B. 16
• C. 30
• D. 64

Question 4

A device sends data to memory at 16 × 10⁶ bytes per second through a DMA controller in cycle-stealing mode, moving 4 bytes in each DMA cycle. One memory cycle takes 100 ns. The fraction of memory cycles stolen by the DMA controller is:

• A. 64%
• B. 40%
• C. 20%
• D. 10%

Question 5

A system has an L1 cache with 2 ns hit time and a 10% miss rate. On an L1 miss the L2 cache is accessed in 10 ns, with a local miss rate of 20%. On an L2 miss the main memory is accessed in 100 ns. Using AMAT = hit time + miss rate × miss penalty at each level, the average memory access time is:

• A. 5.0 ns
• B. 4.0 ns
• C. 6.0 ns
• D. 12.0 ns

Answers and explanations

1. C. The cache has 32 KB / 64 B = 512 lines. With 4 ways there are 512 / 4 = 128 sets, so the index needs 7 bits. The offset needs 6 bits for 64 bytes. Tag = 32 − 7 − 6 = 19 bits. A direct-mapped cache of the same size would have a 9-bit index and a 17-bit tag, which is option A.
2. D. The stall cycles per instruction = 0.25 × 0.60 × 2 = 0.30. So CPI = 1 + 0.30 = 1.30. Option B comes from charging the stall to every branch, taken or not.
3. A. There are 2⁴ = 16 opcode values and 14 are used for three-operand instructions, which leaves 2. Each leftover value, combined with the 4-bit extension field, gives 2⁴ = 16 distinct two-operand opcodes, so 2 × 16 = 32 in total.
4. B. The device delivers 16 × 10⁶ / 4 = 4 × 10⁶ words per second. Each word takes one 100 ns memory cycle, so the DMA controller uses 4 × 10⁶ × 100 × 10⁻⁹ = 0.4 of every second, which is 40% of the memory cycles.
5. A. The L1 miss penalty is the time to get the block from L2 or beyond: 10 + 0.20 × 100 = 30 ns. So AMAT = 2 + 0.10 × 30 = 5 ns.

How to prepare computer organisation

• Practise the address-breakdown template: offset bits = log₂(block size), index bits = log₂(number of sets), tag = address bits − index − offset. Do it for direct-mapped, set-associative and fully associative caches until it is automatic.
• Know the hazard types and fixes: structural, data (RAW, WAR, WAW) and control hazards, with forwarding and stalls. Draw the pipeline diagram for any code fragment and count the stall cycles.
• Learn instruction encoding by working problems: count the bits for opcode, registers, immediates and addressing modes, and practise the expanding-opcode method from Question 3.
• Compare I/O modes: programmed I/O, interrupt-driven and DMA (burst, cycle stealing and transparent), with the arithmetic for transfer time and CPU involvement.
• Write units in every line. Bits versus bytes, KB versus 1000 bytes, ns versus µs: the section is full of questions with a correct method and a wrong unit.
• Read the data-path questions slowly. Micro-operation timing and control-signal questions are less frequent but precise.

Computer organisation builds on digital logic and connects to paging and the TLB in operating systems. The GATE CSE preparation guide suggests how to order these sections, and previous year papers and mock tests explains how to use official papers for practice.

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